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EP3C120F484I7N

EP3C120F484I7N
FPGA Cyclone® III Family 119088 Cells 437.5MHz 65nm Technology 1.2V 484-Pin FBGA

PARTS NO.	MFG	DATE CODE	QTY	DESC
EP3C120F484I7N	ALTERA	2018+	20900	ROHS & ORIGINAL PACKAGE

Product Technical Specifications

EU RoHS	Compliant
ECCN (US)	3A991
Family Name	Cyclone® III	Family Name describes the family name for the product. It is mainly the name noted in the beginning of the datasheet.
User I/Os	283	Maximum Number of User I/Os is Total number of user I/O ports available.
Process Technology	65nm	Process Technology describes the manufacturing process used to fabricate the integrated circuit, specified in the transistor technology, the minimum transistor gate length, and the connecting metal layers for the circuit elements.
Number of I/O Banks	8	Number of I/O Banks is Input/output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including several high-performance different.
Operating Supply Voltage (V)	1.2	Typical Operating Supply Voltage describes the supply voltage at which a device is specified to operate in compliance with the applicable device specification.
Logic Elements	119088	Device Logic Cells is Main elements, which combine to make the logic unit.
Number of Multipliers	288 (18x18)	Number of Multipliers describes the Total number of multipliers may vary according to the multiplier mode used.
Program Memory Type	SRAM	Program Memory Type describes the different types of memory technologies used in electronic devices.
Embedded Memory (Kbit)	3888	RAM Bits describes the size of random access memory.
Total Number of Block RAM	432	Total Number of Block RAM describes the total amount of block RAM memory which depends on the size of FPGA.
IP Core	10 Gigabit Ethernet MAC\|Viterbi Compiler, Low-Speed/Hybrid Serial Decoder\|SpeedView Enabled JPEG Encoder (SVE-JPEG-E)\|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz\|V1 ColdFire	Supported IP Core describe the IP Core that the FPGA can support.
Provider Name	Altera/Freescale/CAST, Inc/MorethanIP/PLDA	Supported IP Core Manufacture describe the IP Core vendor that the FPGA can support.
Device Logic Units	119088	Device Logic Units describes the Main number of units found in the PDF.
Number of Global Clocks	20	Number of Global Clocks describes the number of global clock lines that are combined into a single global clock network that is accessible throughout the entire device. The clock network is optimized to minimize skew, providing clock, clear, and reset signals to all resources.
Device Number of DLLs/PLLs	4	Device Number of DLLs/PLLs describes the number of DLLs/PLLs in the chip.
Programmability	No	Programmability describes the ability to make programming for any device in order to achieve especial task.
Reprogrammability Support	No	Reprogrammability Support describes if the chip can be reprogrammed for many times.
Copy Protection	Yes	Copy Protection is specifies level of Protection for the chip from copying software design or not.
Opr. Frequency (MHz)	437.5	Maximum Internal Frequency describes the speed (in MHz) at which the device can perform operations or data transfers internally. Once the data is in the device, some type of processing (read, write, move, etc.) takes place.
In-System Programmability	No	In System Programmability means that the device can be programmed while it is mounted on the circuit board with the other components. There is no need to disconnect the device for reprogramming.
Speed Grade	7	Speed Grade describes the Speed Frequency for the integrated Circuit.
Differential I/O Standards	HSTL-18\|SSTL-2\|SSTL-18\|RSDS\|LVPECL\|LVDS\|HSTL-15\|HSTL-12	Differential I/O Standards Supported describes types of differential I/O standards that FPGA can support.
Single-Ended I/O Standards	HSTL\|LVCMOS\|LVTTL\|PCI\|PCI-X\|SSTL	Single-Ended I/O Standards Supported describes types of Single-Ended I/O standards that FPGA can support.
External Memory Interface	DDR2 SDRAM\|QDRII+SRAM	External Memory Interface describes types of memory interface that FPGA can support.
Minimum Operating Supply Voltage (V)	1.15	Minimum Operating Supply Voltage describes the minimum supply voltage at which a device is specified to operate in compliance with the applicable device specification.
Maximum Operating Supply Voltage (V)	1.25	Maximum Operating Supply Voltage describes the maximum supply voltage at which a device is specified to operate in compliance with the applicable device specification.
I/O Voltage (V)	1.2\|1.5\|3.3\|2.5\|1.8	I/O Voltage is device supporting number of I/O standard on external input or output pin to make it's easer to interface to high speed devices, I/O standard is selected when CPLD is programmed, These input output standard have varying voltage levels to give good performance.
Minimum Operating Temperature (°C)	-40	Minimum Operating Temperature describes the minimum temperature that the device can function correctly while working.
Maximum Operating Temperature (°C)	100	Maximum Operating Temperature describes the maximum temperature that the device can function correctly while working.
Supplier Temperature Grade	Industrial	Supplier Temperature Grade describes the applications or environment that the device can be used in like commercial, industrial and military.
Tradename	Cyclone	Tradename describes the official name under which a company does business. It is also known as a doing business as name, assumed name, or fictitious name. A trade name does not afford any brand name protection or provide you with unlimited rights for the use of that name. However, registering a trade name is an important step for some but not all businesses.
Pin Count	484	Pin Count describes number of leads attached to package body or number of contact points for each component.
Supplier Package	FBGA
Standard Package Name	BGA
Mounting	Surface Mount
Package Height	1.75
Package Length	23
Package Width	23
PCB changed	484
Lead Shape	Ball