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K4B4G0846D-BYK0000

K4B4G0846D-BYK0
DRAM Chip DDR3 SDRAM 4G-Bit 512Mx8 1.35V 78-Pin F-BGA


PARTS NO.
MFG
DATE CODE
QTY
DESC
K4B4G0846D-BYK0SAMSUNG
2018+
93000
ROHS & ORIGINAL PACKAGE



Descriptions

  •  

  • The 4Gb DDR3 SDRAM D-die is organized as a 512Mbit x 8 I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1866Mb/sec/pin (DDR3- 1866) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK\ falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS\) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS\/CAS\ multiplexing style. The DDR3 device operates with a single 1.35V (1.28V-1.45V) and 1.5V (1.425V-1.575V) power supply and 1.35V (1.28V-1.45V) and 1.5V (1.425V-1.575V) VDDQ. The 4Gb DDR3 D-die device is available in 78ball FBGAs (x8).

    Key Features

    • JEDEC standard 1.35V (1.28V-1.45V) and 1.5V (1.425V-1.575V)

    • Vddq = 1.35V (1.28V-1.45V) and 1.5V (1.425V-1.575V)

    • 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin,933MHz fCK for 1866Mb/sec/pin

    • 8 Banks

    • Programmable CAS Latency (posted CAS) : 11

    • Programmable Additive Latency: 0, CL-2 or CL-1 clock

    • Programmable CAS Write Latency (CWL) = 8 (DDR3-1600)

    • 8-bit pre-fetch

    • Burst Length: 8 (Interleave without any limit, sequential with starting address "000" only), 4 with tCCD = 4 which does not allow seamless read or write

    • Bi-directional Differential Data-Strobe

    • Internal (self) calibration: Internal self-calibration through ZQ pin (RZQ: 240 ohm ± 1%)

    • On Die Termination using ODT pin

    • Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C < Tcase ≤ 95°C

    • Asynchronous Reset

    • Package: 78 balls FBGA -x8

    • All of Lead-Free products are compliant for RoHS

    • All of products are Halogen-free

       

 

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